The metallization process in semiconductor technology is well-known in the art. This process begins in the masking area where contacts, i.e. small holes, are etched through all of the surface layers down to the active regions of the chip. Following contact masking, a thin layer of conducting material is deposited by sputtering, CVD techniques, or vacuum evaporation over the entire wafer. The unwanted portions of this layer are removed by patterning, i.e. photomasking and etch procedures. This step leaves the surface covered within thin lines of conductor.
Patterning errors can cause warped or misaligned patterns that result in undesirable electrical characteristics. Hence, the patterning process is critical to ensuring a satisfactory product. Alignment and exposure continue to be at the heart of patterning.
Two important parameters must be considered when photomasking. The first parameter is the aligner's ability to produce a particular size image, i.e. its resolution capability. The second parameter is the aligner's ability to place images in correct relationship to one another, i.e. its registration capability.
During the photomasking process, an optical phenomena, diffraction, occurs which causes printing to vary from one section of the circuit to another. Diffraction is due to the bending effects of a wave of energy as it passes the opaque edge of a mask. Improvement of aligners has been achieved by using shorter wavelengths which lessen the diffraction effect. However, undesirable resolution and registration still occur even with shorter wavelengths.
For example, if a circuit is core limited, i.e., having lots of gates connected with metal lines, then the printing of lines in the circuit remains homogeneous. However, if the circuit has one section which is heavily populated with lines and another section which is less heavily populated with lines (hereinafter called lonely lines), then the width of the lines and the roughness of the edges of the lines vary from one section to another because of this diffraction phenomenon. As circuits become smaller, the undesirability of varying line size dramatically increases. For example, the difference in line size in one micron technology is probably about 0.05 microns which is approximately a 2 percent difference in size. But at one-half micron technology, the approximate size of the effect is still the same, but the difference is now approximately 10 percent, which is unacceptable.
Etching in semiconductor processing may also entail inherent limitations due to a circuit's physical layout. An ideal anisotropic etch leaves vertical walls in the resist and metal layers. However, because the etching chemical dissolves the top of the wall for a longer time than the bottom, the resulting hole is wider at the top than at the bottom. Hence, the etch is isotropic. This etch undesirably undercuts the metal layer beneath the resist which may result in resist lifting or narrow lines. Dry etching processes, such as reactive ion etching, have decreased undercutting, but have not completely solved this problem.
Dry etch techniques rely in part on material from the masking layer (usually photoresist) to achieve anisotropic profiles. This has the undesirable side effect of making the etch anisotropically sensitive to masking pattern density. Hence, lonely lines in an isolated pattern will etch more isotropic than a heavily populated pattern. Both patterns may exist on the same chip design.
Another problem to be addressed, effectively the mirror image of the problem above, is the issue of microloading where the etching rate of the material is dependent upon the amount of material to be etched. Hence, more surface area to be exposed will take a longer period of time to etch. It logically follows that a part of a chip having different and more densely populated area lines will take a shorter time to etch than an area of less density populated lines.
Another factor to consider during patterning is electromigration. Typically, in circuit layout design, lines are designed to be at one predetermined width, irrespective of their future use. This layout design may create electromigration problems, especially in lines which must carry a heavy load. Long, very thin metal lines, typically formed of aluminum, carrying high currents are particularly prone to electromigration. The high current sets up an electric field in the lead and generates heat. As current and frequency increase, the electromigration resistance goes down. During the electromigration, the aluminum in the lead becomes mobile and begins to diffuse to either end of the lead. Under extreme conditions, the lead itself is severed. In the past, a worst case current density was assumed and all metal lines were made wide enough to carry that current. This is undesirable as line widths become smaller and more functions are put on a single chip.
Another phenomena occuring during patterning is inherent stress due to layering. Because various layers of material are printed on the circuit, all of which may have different coefficients of expansion/contraction and degrees of hardness, an intrinsic stress builds up between these layers. This stress may result in the linear expansion of the softer materials, i.e. generally metals, causing metal voiding even with no voltage. Therefore, stress due to layering may also produce an electrical disconnection.
Therefore, a need arises for a method of improving patterning design for processing.